1. Field of the Invention
The disclosure generally relates to power and timing optimization of an integrated circuit (IC) chip, using an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges.
2. Description of Related Art
Manufacturers of integrated circuits (ICs) seek to reduce, not only, the size of ICs, but also their power consumption. Power consumption of digital integrated circuits consists of two components: dynamic power consumption, associated with active operation of the circuit; and static power consumption, associated with leakage current when the circuit is inactive. Dynamic power consumption refers to the amount of power required to operate a digital circuit, e.g., a logic circuit or latch, and is proportional to value of the supply voltage squared and the frequency of operation. Static power consumption refers to the amount of power consumed by the digital circuit when it is inactive, and is an exponential function of the digital circuit's temperature and voltage.
Digital ICs frequently include a number of standard cells, i.e., standardized digital IC logic circuits or latches, which are characterized by cell libraries. The cell libraries of, for example, a Liberty model, are used during the design phase for the digital ICs and store various operating parameters, e.g., voltage, temperature, timing delay and power consumption ranges.
During the design phase of an IC chip, the cells and their interconnecting pathways may be analyzed in a multidimensional parameterized space, which includes voltage and temperature parameters, to provide a closed timing analysis for the IC chip. A timing performance, as measured by a timing delay, is selected for the IC design from the closed timing analysis.
The manufacture of IC chips to a single IC chip design will result in timing variations among the manufactured IC chips that result from variations of manufacturing process parameters, e.g., chemical mechanical polishing, optical proximity effects, random dopant effects, line-edge roughness, dose and focus variation. Variations in the manufacturing processes can introduce timing variations across chips of a single wafer or across chips from different wafers. Thus, in a population of IC chips manufactured to a single IC chip design, there will be a statistical distribution of subpopulations of IC chips that show smaller timing delays, i.e., fast IC chips, and larger timing delays, i.e., slow IC chips.
During operation, cells of IC chips manufactured from IC technologies, which exhibit temperature inversion, are associated with a negative coefficient of delay with respect to temperature. Thus, as temperatures increase for the cells of an IC chip exhibiting temperature inversion, the timing delay becomes smaller. In contrast, IC chips manufactured from IC technologies, which do not exhibit temperature inversion, show greater timing delays with increasing temperature.
At lower temperatures, cells of an IC chip using an IC technology that shows temperature inversion will have a greater timing delay. When supplied with a low driving voltage, these IC chips may not meet a timing delay performance. To meet a requirement for the timing delay performance, the IC chips can be driven at a high voltage at the lower temperatures. However, driving the IC chips at a high voltage results in increased dynamic and static power consumption. Alternatively, only those IC chips having a sufficiently high performance at the lower temperatures may be selected from a population of manufactured IC chips to meet the timing delay performance. This selection necessarily results in a smaller number of IC chips that are available.
At higher temperatures, cells using an IC technology that shows temperature inversion will show both increased dynamic and static power consumption, because voltage needs to be raised in order to meet performance at low temperature. This increased voltage causes higher active and leakage power.
There remains a need to optimize power and timing of an integrated circuit (IC) chip, using an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power and timing delay performances across lower and higher temperature ranges.